With the on-going development of the integrated circuit technology, particularly the continuous reduction of the device size in scale, various key parameters of the device such as the threshold voltage are also reduced accordingly, the advantages of reduction in the power consumption and increase in the integration can promote the enhancement of the overall performance of the device. However, at the same time, the device drive capability is limited by the traditional technology of silicon material, the carrier mobility is low, thus a problem of a relatively low device drive capability is confronted with. Accordingly, the high mobility channel device finds a very important application prospect in the future.
For existing high mobility channel devices, generally Si1-xGex or Si1-xCx is adopted as a stressed source/drain region for applying a stress to the Si channel region, or these materials are directly adopted as the substrate and the channel region. The hole mobility may be further enhanced by introducing a compressive strain into Si1-xGex, and correspondingly the electron mobility may be further enhanced by introducing a tensile strain into Si1-xCx. However, the lattice constants of the two materials are not sufficiently different from that of Si, they can only provide a limited strain, thus can hardly be applied to the device requiring a higher driving capability.
One alternative material is a GeSn alloy, the thin film thereof has a high carrier mobility, and the band structure of the alloy can be adjusted by adjusting the concentration of Sn, thus the material is widely applied to advanced CMOS devices and photoelectronic devices.
However, it need molecular-beam epitaxy or CVD to form the traditional GeSn alloy, which is still not mature or not compatible with CMOS currently. Besides, since Sn has a very low equilibrium solid solubility in Ge, it is difficult to obtain the Ge1-xSnx with the concentration of Sn higher than 1% by conventional processes.
In addition, other high mobility materials such as GaAs and InSb also have the same problem and can hardly be compatible with the Si-based CMOS process.
On another hand, with the decrease in the channel length of a conventional MOSFET, the leakage current will increase accordingly. Particularly in the technology below 30 nm, the device leakage current is significantly increased, causing the power consumption of the entire device to increase unstoppably. One way to reduce the device power consumption is to adopt a new type of tunnel field-effect transistor (TFET) structure, wherein, by adding a tunnel dielectric layer between the source and the channel region, the leakage current is effectively decreased, and the chip power consumption is greatly reduced. However, when the size is continuously reduced to below 22 nm, the existing common TFET drive current is 3-4 orders of magnitude lower than the conventional MOSFET drive current, rendering that reduction in the power consumption and increase in the drive capability can not be balanced, and the overall performance of the device can only have a limited increase.